JTAG Header for FPGA/CPLD Applications (Comcom Electronics Standard) pinout

connector wiring scheme

Pin	Name	Description
1	TCK	Test Clock
2	GND	Ground
3	TDI	Test Data Input
4	GND	Ground
5	TDO	Test Data Output
6	VCC	Power Supply
7	TMS	Test Mode Select
8	TRS	Test Reset

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Pinouts.ru > Some peripheral devices pinouts > Pinout of JTAG Header for FPGA/CPLD Applications (Comcom Electronics Standard) and layout of connector	Is it correct?:	should be correct
Source(s) of this and additional information: www.comcom.ru and Sandy	2 reports
Last updated 2008-06-28 21:56:54. Edit this page.	Is this document correct or incorrect? What is your opinion?

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