Memory slots and cards connectors pinouts
SO DIMM=Small Outline Dual Inline Memory Module
Pin Non-Parity Parity Description
1VSSVSSGround
2DQ0DQ0Data 0
3DQ1DQ1Data 1
4DQ2DQ2Data 2
5DQ3DQ3Data 3
6DQ4DQ4Data 4
7DQ5DQ5Data 5
8DQ6DQ6Data 6
9DQ7DQ7Data 7
10VCCVCC+5 VDC
11PD1PD1Presence Detect 1
12A0A0Address 0
13A1A1Address 1
14A2A2Address 2
15A3A3Address 3
16A4A4Address 4
17A5A5Address 5
18A6A6Address 6
19A10A10Address 10
20n/cPQ8Data 8 (Parity 1)
21DQ9DQ9Data 9
22DQ10DQ10Data 10
23DQ11DQ11Data 11
24DQ12DQ12Data 12
25DQ13DQ13Data 13
26DQ14DQ14Data 14
27DQ15DQ15Data 15
28A7A7Address 7
29A11A11Address 11
30VCCVCC+5 VDC
31A8A8Address 8
32A9A9Address 9
33/RAS3RAS3Row Address Strobe 3
34/RAS2RAS2Row Address Strobe 2
35DQ16DQ16Data 16
36n/cPQ17Data 17 (Parity 2)
37DQ18DQ18Data 18
38DQ19DQ19Data 19
39VSSVSSGround
40/CAS0CAS0Column Address Strobe 0
41/CAS2CAS2Column Address Strobe 2
42/CAS3CAS3Column Address Strobe 3
43/CAS1CAS1Column Address Strobe 1
44/RAS0RAS0Row Address Strobe 0
45/RAS1RAS1Row Address Strobe 1
46A12A12Address 12
47/WEWERead/Write
48A13A13Address 13
49DQ20DQ20Data 20
50DQ21DQ21Data 21
51DQ22DQ22Data 22
52DQ23DQ23Data 23
53DQ24DQ24Data 24
54DQ25DQ25Data 25
55n/cPQ26Data 26 (Parity 3)
56DQ27DQ27Data 27
57DQ28DQ28Data 28
58DQ29DQ29Data 29
59DQ31DQ31Data 31
60DQ30DQ30Data 30
61VCCVCC+5 VDC
62DQ32DQ32Data 32
63DQ33DQ33Data 33
64DQ34DQ34Data 34
65n/cPQ35Data 35 (Parity 4)
66PD2PD2Presence Detect 2
67PD3PD3Presence Detect 3
68PD4PD4Presence Detect 4
69PD5PD5Presence Detect 1
70PD6PD6Presence Detect 6
71PD7PD7Presence Detect 7
72VSSVSSGround
72 pin SO DIMM connector layout
72 pin SO DIMM connector
at the computer
According to 1 reports in our database (1 positive and 0 negative) this pinout should be correct.

Is this pinout
SO DIMM (72 pin) visual pinout:
SO DIMM (72 pin) diagram
click to enlarge
Source(s) of this and additional information: Various productsheets at IBM Memory Products, from Hardware Book, Mark Brown, Jim Burd
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