96 pin DIN 41612 (3x32) female connector layout
96 pin DIN 41612 (3x32) female connector
at the backplane
VMEbus is a computer bus standard originally developed for the Motorola 68000 line of CPUs, but later widely used for many applications.

VMEBus is physically based on the Eurocard sizes, mechanicals and connectors, but uses its own signalling system, which Eurocard does not define. It was first developed in 1981, and continues to see widespread use today.

In many ways the VMEbus is the pins of the 68000 run out onto a backplane. In most cases this is a bad design, because it limits you to systems similar to the chipset the bus was originally designed for. (For instance, the ISA bus is still useful only for Intel chips). However one of the key features of the 68000 was a flat 32-bit memory model, free of memory segmentation and other "anti-features". The result is that while VME is very 68000-like, the 68000 is generic enough to make this a non-issue in most cases.

Like the 68000, VME uses separate data and address buses, both 32-bits. In the case of the 68000 the address bus was actually 24-bits and the data bus 16-bits (although it was 32/32 internally), but the designers were already looking towards full 32-bit implementations. In order to allow both widths of buses to be used, VME uses two different Eurocard connectors, the P1 and P2. P1 contains three rows of 32 pins each, implementing the first 24-bits of the address and 16-bits of the data buses, along with all of the control signals. The P2 contains one more row, which includes the remaining 8 address and 16 data pins.

In order to control the bus a set of nine lines known as the arbitration bus is used. All communications are controlled by the card inserted in slot one of the Eurocard chassis, known as the arbiter module. In general use the cards will request access to the bus by holding the bus request in lines of the arbitration bus low to indicate their slot number. When the arbiter module frees the bus it scans these lines to see if there are any held low. If so, it pulls the bus busy line low to indicate the bus is going busy again, and writes the card number back out on the bus grant out lines.

At this point the numbered card has gained access to the bus. To write data the card writes the address and data to the bus, and then pulls the address strobe line and the two data strobe lines low to indicate the data is ready, and then pulls the write pin to indicate the operation. There are two data strobes so the cards can indicate if the data is 8, 16, or 32 bits (or 64 in VME64). The card at the indicated address on the bus then reads the data and pulls the data transfer acknowledge line when it is complete (or the bus error line if need be). Reading data is essentially the same, but the controlling card places only the address on the bus and pulls the READ pin. The other card then writes the data and pulls the data strobe pins when the data is ready. This signalling scheme is asynchronous, meaning that there is no overall clock signal as there is in synchronous buses such as PCI.

VME also includes an interrupt bus, supplying all seven of the 68000"s interrupt pins. When an interrupt is supplied the arbiter module writes the interrupt level back out to the address bus to tell which interrupt is being handled. Note that there is no concept of card number in this case, because cards will often share interrupts. The excessive number of interrupt levels has often been pointed to as one of the few examples of overdesign in the 68000, and it makes even less sense in the case of a bus.

Note that in VME all transfers are DMA and every card is a master (or slave). In most bus standards there is a considerable amount of complexity added in order to support various transfer types and master/slave selection. For instance, in the ISA bus both of these features had to be added on top of the already existing "channels" model where all communications was handled by the host CPU. This makes VME considerably simpler at a conceptual level while being more powerful, although it requires somewhat more complex controllers on each card in order to work.

J=Jack (Backplane), P=Plug (Board)

P1/J1 (Required)

Pin Name
a1D00
a2D01
a3D02
a4D03
a5D04
a6D05
a7D06
a8D07
a9GROUND
a10SYSCLK
a11GROUND
a12DS1*
a13DS0*
a14WRITE*
a15GROUND
a16DTACK*
a17GROUND
a18AS*
a19GROUND
a20IACK*
a21IACKIN*
a22IACKOUT*
a23AM4
a24A07
a25A06
a26A05
a27A04
a28A03
a29A02
a30A01
a31-12V
a32+5V
Pin Name
b1BBSY*
b2BCLR*
b3ACFAIL*
b4BG0IN*
b5BG0OUT*
b6BG1IN*
b7BG1OUT*
b8BG2IN*
b9BG2OUT*
b10BG3IN*
b11BG3OUT*
b12BR0*
b13BR1*
b14BR2*
b15BR3*
b16AM0
b17AM1
b18AM2
b19AM3
b20GROUND
b21SERCLK*
b22SERDAT*
b23GROUND
b24IRQ7*
b25IRQ6*
b26IRQ5*
b27IRQ4*
b28IRQ3*
b29IRQ2*
b30IRQ1*
b31+5V STDBY
b32+5V
Pin Name
c1D08
c2D09
c3D10
c4D11
c5D12
c6D13
c7D14
c8D15
c9GROUND
c10SYSFAIL*
c11BERR*
c12SYSRESET*
c13LWORD*
c14AM5
c15A23
c16A22
c17A21
c18A20
c19A19
c20A18
c21A17
c22A16
c23A15
c24A14
c25A13
c26A12
c27A11
c28A10
c29A09
c30A08
c31+12V
c32+5V

P2/J2 (Optional)

Pin Name
b1+5v
b2GROUND
b3RESERVED
b4A24
b5A25
b6A26
b7A27
b8A28
b9A29
b10A30
b11A31
b12GROUND
b13+5V
b14D16
b15D17
b16D18
b17D19
b18D20
b19D21
b20D22
b21D23
b22GROUND
b23D24
b24D25
b25D26
b26D27
b27D28
b28D29
b29D30
b30D31
b31GROUND
b32+5V

*) Active Low

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