Apple II slot specification users reports and reviews

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There are 3 approved reports in our database

Date	User opinion	Comment	Content Revision	Approved by moderator?
	INCORRECT	Data bus signals D[0..7] are reversed		APPROVED
2010-01-21 01:49:26	ERROR FIXED	Pin 42 is D7; 43 is D6; 42 is D5; 43 is D4; 44 is D3; 45 is D2; 46 is D1; 47 is D0; you have them reversed in the pinout.	rev. 2	APPROVED
2010-08-17 04:24:48	ERROR FIXED	Data bus is flipped: The correct order has pin 42 = D7, 43 = D6, all the way down to 49 = D0. Confirmed in actual practice on a //e, as well as with the Apple II Reference Manual "red book" (Jan 1978) page 149, and the Apple IIgs Hardware Reference 2nd Ed (page 173).	rev. 2	APPROVED

History of users contributions

Date	Author	Content Revision	Comment

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